In conventional verification techniques, users normally have to specify the clock sources after the electronic design is compiled into an EDA (electronic design automation) tool. The EDA tool may automatically identify the CDC (clock domain crossing) paths based on the clock sources specified by the users. The EDA tool may then run structural rule checker which reports warnings and/or errors according to a configured rule set of structural rules. Users may decide whether to modify the RTL designs or bypass the warnings and/or errors according their design intent. After the structural rule checking, EDA tool may inject a CDC-effect module with the introduction provided by users. In some cases, users may allow the EDA tool to inject the CDC-effect module along a clock domain crossing path if the CDC path is simple or satisfies the structural rules. In some other cases, users may have to instruct the EDA tool where to inject the CDC-effect module if the CDC path is complex as decided by the users. Users may then verify the electronic circuit of interest via either simulation or verification techniques with the CDC-effect module injected or which circuit component is to be replaced with a CDC-effect module in the RTL (register transfer level) design. In these approaches, users may need to identify the CDC paths in the RTL design, decide where the inject the CDC-effect module along a CDC path, provide instructions to the EDA tool to modify intermediate design data of the electronic design for verification, and run the same target properties to verify the electronic design.
Users cannot, however, randomly select any circuit components to replace with CDC-effect modules. Rather, CDC-effect module injection requires an insurmountable amount of time, efforts, and expertise on the part of the designers in order to correctly accommodate the CDC-effect models during design verification or simulation. In some cases where structural rules are involved in the verification of an electronic design, EDA (electronic design automation) tools may not necessarily report structural connectivity. This lack of structural connectivity further exacerbates the difficulties in verification of electronic designs having cross clock domain paths. Moreover, due to the increasingly more clock domains and complexities in modern electronic designs, it is extremely difficult, if not entirely impossible, to determine correct locations to inject CDC effects or CDC effect models or to avoid the overly pessimistic, overly optimistic, or erroneous user-defined CDC effect injection in order to correctly account for CDC effects in verification of electronic designs at early design stages.
To improve the accuracy, coverage of conventional verification or simulation techniques that determine whether an electronic design conforms to the specification, there exists a need for methods, systems, and computer program products for verifying an electronic design with clock domain crossing paths.